max / everycycle
1 file changed,
+29 insertions,
-5 deletions
| @@ -36,7 +36,7 @@ | |||
| 36 | 36 | | Component | Choice | Approx | Notes | | |
| 37 | 37 | |---|---|---|---| | |
| 38 | 38 | | CPU | **AMD EPYC 4565P** (16c/32t "Zen 5", AM5) | ~$700–800 | 4.30 base / 5.70 boost, 64 MB L3, 170 W, 2× DDR5-5600, 28 PCIe Gen 5 lanes. Sized for throughput: clean builds, container builds, the ISO's zstd pass. See the CPU note below for why this and not a Ryzen 9950X. **Ceiling: EPYC 4005 stops at 16 cores**, so if throughput ever binds the answer is a new machine, not a new CPU — acceptable for a declared stepping stone | | |
| 39 | - | | Board | **ASRock Rack B650D4U** (base variant) | ~$400–450 | mATX server board. **AST2600 BMC** with IPMI 2.0, iKVM, vMedia, dedicated management LAN. Base variant chosen over -2L2T/-2L2T/BCM specifically because **it is the only one with two M.2 slots** | | |
| 39 | + | | Board | **ASRock Rack B650D4U** (base variant) | ~$400–450 | mATX server board. **AST2600 BMC** with IPMI 2.0, iKVM, vMedia, dedicated management LAN. Base variant chosen over -2L2T/-2L2T/BCM because **it is the only one with two M.2 slots**; see the networking note for why its 1 GbE is not a compromise | | |
| 40 | 40 | | RAM | 2× 48 GB DDR5 ECC UDIMM (96 GB) | ~$450 | 1 DPC runs 5600; 2 DPC drops to 3600. Two slots stay empty on purpose | | |
| 41 | 41 | | Storage 1 | 2 TB NVMe on M2_1 (PCIe 5.0 x4) | ~$180 | **xfs** root. Not ZFS — see the note in `mm-v1-bom.md` | | |
| 42 | 42 | | Storage 2 | 4 TB NVMe on M2_2 (PCIe 4.0 x4) | ~$280 | Raw XFS scratch: kv-cache overflow later, container build scratch from day one | | |
| @@ -173,6 +173,32 @@ | |||
| 173 | 173 | - **B6** (frontier-size with CPU offload) — **does not fit.** Two DDR5 channels is ~80–90 GB/s | |
| 174 | 174 | against ~358 GB/s for 8-channel DDR5-5600. CPU-offload work belongs to the replacement. | |
| 175 | 175 | ||
| 176 | + | ## Networking: 1 GbE now, 10 GbE deferred into PCIE7 | |
| 177 | + | ||
| 178 | + | The board comes in three variants and the choice is a three-way trade between M.2 slots, | |
| 179 | + | 10 GbE and cost. Only the base `B650D4U` has **two** M.2 slots; both 10 GbE variants have one, | |
| 180 | + | because the 10 GbE controller eats the FCH lanes M2_2 would use. | |
| 181 | + | ||
| 182 | + | Measured on the LAN 2026-07-25 rather than assumed: | |
| 183 | + | ||
| 184 | + | - **fw13**: USB adapter, linked at **1000 Mb/s**. A Framework 13 has no easy 10 GbE path | |
| 185 | + | short of a Thunderbolt adapter. | |
| 186 | + | - **astra**: `enP3p3s0f0` and `f1` are on the **ixgbe** driver, so that is Intel 10 GbE | |
| 187 | + | silicon — but `f0` is linked at **1000 Mb/s** and `f1` is down. | |
| 188 | + | ||
| 189 | + | So 10 GbE hardware exists on the LAN and nothing is actually running at 10 GbE. More to the | |
| 190 | + | point, the traffic that would justify it is moving multi-GB ISOs and images to wherever a USB | |
| 191 | + | stick gets written, which is fw13, which is 1 GbE-limited regardless. | |
| 192 | + | ||
| 193 | + | **Decision: take the base board, keep both native M.2, and leave PCIE7 empty.** If a 10 GbE | |
| 194 | + | path later proves worth having, PCIE7 (Gen 5 ×4) takes a NIC with room to spare — 10 GbE needs | |
| 195 | + | a fraction of that. Deferring costs nothing and avoids paying a board premium plus an M.2 | |
| 196 | + | adapter for a link that currently has no peer running at speed. | |
| 197 | + | ||
| 198 | + | **Constraint on that later NIC: it must be ×4 *mechanical*.** PCIE7 is ×4 mechanically, so an | |
| 199 | + | Intel X550-T2 (×4) fits and an X710-T2L (×8) does not. An X550 also pairs with the same | |
| 200 | + | `ixgbe` driver astra already runs, which is a known-good story rather than a new one. | |
| 201 | + | ||
| 176 | 202 | ## The bench is not a control until it is characterized | |
| 177 | 203 | ||
| 178 | 204 | "All-new means known-good" is the right instinct with the wrong mechanism. New parts have | |
| @@ -233,10 +259,8 @@ | |||
| 233 | 259 | - **Does the board QVL cover DDR5 ECC UDIMM with EPYC 4005?** The manual hedges: "Memory | |
| 234 | 260 | support is to be validated." ECC UDIMM plus a server board plus a not-quite-Ryzen CPU is | |
| 235 | 261 | exactly where QVL matters. Resolve before buying DIMMs. | |
| 236 | - | - **1 GbE vs 10 GbE.** The base variant is 2× 1 GbE. The existing LAN (192.168.1.x, consumer | |
| 237 | - | gateway) is almost certainly 1 GbE, so 10 GbE would have nothing to talk to, and PCIE7's | |
| 238 | - | Gen5 x4 can take a 10 GbE NIC later if that changes. Confirm the LAN before paying for | |
| 239 | - | -2L2T. | |
| 262 | + | - ~~1 GbE vs 10 GbE~~ **settled 2026-07-25 by measuring the LAN** — see the networking | |
| 263 | + | section. Base board, PCIE7 left empty for a future ×4-mechanical NIC. | |
| 240 | 264 | - **OpenBMC.** `crates/bmc-agent` says it runs on "an OpenBMC fork on Aspeed AST2600-class | |
| 241 | 265 | hardware". This board has the AST2600 but ships ASRock's vendor IPMI firmware, and vendor | |
| 242 | 266 | BMC images are typically signed. If it cannot be replaced, `bmc-agent` retargets |